1. Field of the Invention
The present invention relates to increase in performance of MOS transistors.
2. Description of the Background Art
With higher integration of LSI circuits, the gate length of MOS transistors which are constituents of the LSI circuit has been reduced, and MOS transistors having a gate length of 0.25 .mu.m or less are becoming commercially practical. Such a short gate length causes punch-through to be pronounced, that is, a drain depletion layer extending into a source results in a leak current flow independently of gate control.
To prevent such punch-through, a higher impurity concentration between the source and drain is required so as to prevent extension of the drain depletion layer. However, the increase in the impurity concentration increases a threshold voltage (V.sub.th) of the MOS transistors.
High-performance LSI circuits which operate at low voltages are required in the field of portable equipments for which market expansion is expected in the future. FIG. 38 is a graph plotting circuit delay versus threshold voltage for various power supply voltages V.sub.DD in a circuit including an odd number of series-connected three-input NAND gates formed by MOS transistors (R. H. Dennard, et al., "Power-Supply Considerations For Future Scaled CMOS Systems", 1987 Symposium on VLSI Technology, Systems and Applications, Taipei, Taiwan, P.188). It is apparent from the graph that the MOS transistor threshold voltage exerts a greater impact on the circuit delay with decrease in power supply voltage V.sub.DD. Thus, a need arises to reduce the MOS transistor threshold voltage.
A structure including a punch-through stopper layer and a buried layer has been conventionally proposed to provide a high punch-through resistance and a low threshold voltage in the MOS transistors. FIG. 39 is a cross-sectional view of an N-channel buried type MOS transistor 200 disclosed by Nagai et al., "Extended Abstracts of the 1992 Solid State Devices and Materials".
Referring to FIG. 39, a punch-through stopper layer 20 having a positive impurity concentration of 1.times.10.sup.18 cm.sup.-3 or more is formed on an upper surface of a P-type semiconductor layer (well) 1. A buried layer 3 is formed on an upper surface of the punch-through stopper layer 20 in a channel region. The buried layer 3 is sandwiched between an N-type source region 41 and an N-type drain region 42.
A gate oxide film 4 is formed on the buried layer 3, and a gate electrode 5 is opposed to the buried layer 3, with the gate oxide film 4 therebetween. Sidewalls 8 are located on the both sides of the gate oxide film 4 and gate electrode 5.
The source region 41 and the semiconductor layer 1 receive 0 V (or are grounded), and a voltage of about 2.5 V is applied to the drain region 42. With the gate electrode 5 at a potential of 0 V, the channel region is depleted and has a low electron concentration. Thus, no current flows between the source region 41 and the drain region 42.
With the gate electrode 5 at a potential of 2.5 V, the channel region has an increased electron concentration and there is a current flow between the source region 41 and the drain region 42. In this manner, the NMOS transistor 200 operates as a switching device depending on the potential at the gate electrode 5.
As stated above, the channel length of 0.5 .mu.m or less, with the gate electrode 5 at the potential of 0 V, causes the drain field to extend into the source region 41, resulting in a current flow between the source region 41 and the drain region 42 (punch-through). The punch-through stopper layer 20 is provided to prevent punch-through. The provision of the punch-through stopper layer 20 increases the threshold voltage of surface channel type MOS transistors. To prevent such an increase, the buried layer 3 is formed by counter doping in the channel region to construct a buried channel type MOS transistor, achieving high punch-through resistance and low threshold voltage.
FIG. 40 is a graph showing a profile of impurity concentration versus depth of the NMOS transistor 200 (in section taken along the line T--T of FIG. 39). The reference numerals indicative of respective portions of the curves represent substantial positions of the corresponding regions. The impurity concentrations of the drain regions 42 and punch-through stopper layer 20 exceed 1.times.10.sup.18 cm.sup.-3 at the intersection of the impurity profiles for the drain region 42 and punch-through stopper layer 20.
FIG. 41 is a graph showing a profile of field strength in section taken along the line T--T of FIG. 39. It is understood that the field strength adjacent the junction of the drain region 42 and punch-through stopper layer 20 exceeds 1--10.sup.6 V/cm.
In this fashion, the NMOS transistor 200, including the punch-through stopper layer 20 having a high impurity concentration, has a narrow depletion layer at the PN junction between the drain region 42 and the punch-through stopper layer 20. This increases the resultant electric field, resulting in an increased leak current.